Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldins.b Rd:<part>, Rp[disp] 

If (part == b)
      Rd[7:0] = *(Rp+SE(disp12));
else if (part == l)
      Rd[15:8] = *(Rp+SE(disp12));
else if (part == u)
      Rd[23:16] = *(Rp+SE(disp12));
else
      Rd[31:24] = *(Rp+SE(disp12));
 
{p, d} ∈ {0, 1, …, 15}
part ∈ {t, u, l, b}
disp ∈ {-2048, -2047, ..., 2047}

Rev1+

111

Rp

11101

Rd

01

part

disp12

3

4

5

4

2

2

12

2

ldins.h Rd:<part>, Rp[disp] 

If (part == b)
      Rd[15:0] = *(Rp+SE(disp12) << 1);
else
      Rd[31:16] = *(Rp+SE(disp12) << 1);
 
{p, d} ∈ {0, 1, …, 15}
part ∈ {t, b}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

111

Rp

11101

Rd

000

part

disp12

3

4

5

4

3

1

12

Description

This instruction loads a byte or a halfword from memory and inserts it into the addressed byte or halfword position in Rd. The other parts of Rd are unaffected.

Status Flags:

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected